发明名称 Alignment of clock domains in packet networks
摘要 Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points. These steps are continually repeated on new sets of data points created from newly received synchronization packets using the current delay estimate for the expected delay. And a clock domain at the destination is continually aligned with a clock domain at the source based on the current delay estimate for packets traversing the network between the source and destination.
申请公布号 US2004264477(A1) 申请公布日期 2004.12.30
申请号 US20040781164 申请日期 2004.02.18
申请人 ZARLINK SEMICONDUCTOR INC. 发明人 REPKO WILLEM L.;VAN DER VALK ROBERTUS L.;SIMONS PETRUS W.;BARRACK CRAIG
分类号 H04J3/06;(IPC1-7):H04L12/66 主分类号 H04J3/06
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