发明名称 |
Integrated circuit, its fabrication process and memory cell incorporating such a circuit |
摘要 |
This integrated circuit comprises a capacitor (23) formed above a substrate (1) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure (7) for connection to the capacitor. The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.
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申请公布号 |
US2004266099(A1) |
申请公布日期 |
2004.12.30 |
申请号 |
US20040486950 |
申请日期 |
2004.08.20 |
申请人 |
MALLARDEAU CATHERINE;MAZOYER PASCALE;PIAZZA MARC |
发明人 |
MALLARDEAU CATHERINE;MAZOYER PASCALE;PIAZZA MARC |
分类号 |
H01L21/02;H01L21/8242;H01L27/108;(IPC1-7):H01L21/824;H01L29/76;H01L29/94;H01L31/119 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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