| 摘要 |
A data bus of a single-end structure is arranged commonly to a plurality of banks, and a reference data bus transferring reference data providing a criterion of logical level determination of transfer data is arranged corresponding to each bank. For generating a reference potential, a Vref generating circuit is arranged neighboring and corresponding to a DQ circuit band performing input/output of data such that the reference potential required in a data write operation and a data read operation is transmitted to each reference data bus in a concentrated fashion. A semiconductor memory device thus formed transfers data fast with low current consumption without increasing an interconnection layout area.
|
