发明名称 |
Circuit for bit skew suppression in high speed multichannel data transmission |
摘要 |
A deskewing circuit configured to receive a main clock signal wherein data bits are misaligned with respect to the main clock signal. A multiphase clock generator coupled to the main clock to generate N/2 clock phases on the rising edge of the main clock and N/2 clock phases on the falling edge. A plurality of n samplers to generate a first set of N/2 sampled signals on the positive phases and a second set of N/2 sampled signals on the negative phases. A corresponding plurality of n phase selectors to determine which phase is the best for each set of sampled signals and generate the two selected signals corresponding to that phase. A control logic block configured to receive a corresponding plurality of n first control signals. A data bus gathering all said selected signals for further processing, wherein said selected signals are aligned with said reference clock but misaligned with respect to each other.
|
申请公布号 |
US2004264613(A1) |
申请公布日期 |
2004.12.30 |
申请号 |
US20040873772 |
申请日期 |
2004.06.22 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BUCHMANN PETER;NICOT SYLVIE;PEREIRA DAVID |
分类号 |
H04L7/00;H04L7/033;H04L7/04;H04L7/10;H04L25/14;(IPC1-7):H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|