发明名称 |
Latch type sense amplifier method and apparatus |
摘要 |
Disclosed is an apparatus for and a method of overcoming signal delay problems in a read-out path occurring in connection with pipelined memory circuits. A latch type sense amplifier (SA) is used to receive the memory cell logic levels during a pre-charge state in a cycle prior to read-out. Thus, the SA may quickly provide an output signal during a read latch clock cycle. The SA output is passed through a dynamically enabled logic circuit to a latch circuit for holding the receiving logic value for use in the next clock cycle.
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申请公布号 |
US2004264276(A1) |
申请公布日期 |
2004.12.30 |
申请号 |
US20030606587 |
申请日期 |
2003.06.26 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;TOSHIBA AMERICA ELECTRONIC COMPONENTS , INC;KABUSHIKI KAISHA TOSHIBA |
发明人 |
ASANO TORU;DHONG SANG HOO;NAKAZATO TAKAAKI;TAKAHASHI OSAMU |
分类号 |
G11C7/06;G11C7/10;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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