METHOD FOR THE CODING/DECODING OF VLIW CACHED INSTRUCTIONS

摘要

The invention relates to a method for the control of functional units in a processor. During a configuration phase, a series of primary instruction words from the translation of a programme code are subjected to a division into series of instruction word bits, whereby the instruction words controlling the processor during a programme execution are generated with the full instruction word size and buffered in an instruction word memory (cache). According to the invention, the aim of increasing the processor performance in the execution phase by increasing the degree of compression of the primary instruction words into the divided instruction word bits thereof, independent of special features (such as periodicity) of the FIW (Function Instruction Word bit) is achieved, whereby the division of a primary instruction word into a TVLIW (Tagged Very Long Instruction Word) occurs in a first step during the configuration phase and the given TVLIW is transformed into a HVLIW (Headed Very Long Instruction Word) in a second step. A general header is given in the HVLIW. The HVLIW, with the code-compressed structure thereof, replaces all functions of the TVLIW (1).