| 摘要 |
In a processor module (100) having a local software visible data memory (104) and a write through cache (106) connected to an external memory space (150) external to the processor module (100) over a bus (20), a method and apparatus for supplementing the data memory (104) utilizing the write through cache (106) which may comprise: a processor bus interface and memory management unit (110) adapted to detect a processor write operation to a preselected location in the external memory space (150) that is not currently a cached address line, that will cause a cache miss, to decode the write operation to the preselected external memory space location as a RAM emulation write operation and to place in the cache (106) pseudo data at the respective address line in the cache, without executing a fetch and store from the actual external memory location in response to the cache miss. |
