| 摘要 |
An alignment circuit (18) is configured to receive a reference clock signal (ref_clk) derived from a main clock having a period T and successive sets of 2n data bits that are transmitted in parallel on a data bus (26) wherein said data bits are aligned with respect to said reference clock signal but misaligned with respect to each other. It first comprises a plurality of n aligners. Each aligner (49-i) is coupled to said reference clock and a pair of said data bits, referred to as primary bits, one data bit (bit_tdat(i)) having the rank (i) in a determined set and the other being the corresponding data bit (bit_tdat(i+n)) having the rank (i+n) in the set. Each aligner comprises first, second and third shifting means (51-i,52-i,53-i) for shifting said primary data bits to respectively generate respective data bits delayed of one, two and two and half cycles and a multiplexor (50-i) receiving said primary and delayed data bits under the control of three control signals of a first type (recal(i), realign0(i) and realignl(i)) to generate a pair of aligned data bits (tdat_desk(i) & tdat_desk(i+n)). It further comprises a control block (58) coupled to said primary signals and to all pairs of said aligned data bits (tdat_desk(0) to tdat_desk(2n-1) determines the end of the alignment operation and generates a control signal of a second type (enable_test). As a result, said alignment circuit generates 2n data bits (tdat_desk(0) to tdat_desk(2n-1)) that are aligned with said main clock and with each other on a data bus (57). <IMAGE>
|
