Structure of integrated trace of chip package

摘要

A semiconductor die package is disclosed. The die package includes a semiconductor die having a first side and a second side, a vertical transistor, and a bond pad at the first side. A passivation layer having a first aperture is on the first side, and the bond pad is exposed through the first aperture. An underbump metallurgy layer is on and in direct contact with the passivation layer. The underbump metallurgy layer is within the first aperture and contacts the bond pad. A dielectric layer comprising a second aperture is on and in direct contact with the underbump metallurgy layer. A solder structure is on the underbump metallurgy layer and is within the second aperture of the dielectric layer.