发明名称 |
Apparatus and method for testing semiconductors |
摘要 |
A test circuit for testing semiconductors includes a plurality of at least first conductors and second conductors. The first and second conductors are operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors. A plurality of conductive taps are included, each of the taps being connected at a first end to a corresponding first conductor. The test circuit further includes a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps. Each of the switching circuits is configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.
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申请公布号 |
US6836106(B1) |
申请公布日期 |
2004.12.28 |
申请号 |
US20030668561 |
申请日期 |
2003.09.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BRELSFORD KEVIN H.;FILIPPI, JR. RONALD G.;RODBELL KENNETH P.;WANG PING-CHUAN |
分类号 |
G01R31/26;G01R31/28;G11C29/56;(IPC1-7):G01R31/26 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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