发明名称 |
Semiconductor integrated circuit device with a plurality of limiter circuits |
摘要 |
A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.
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申请公布号 |
US6835971(B2) |
申请公布日期 |
2004.12.28 |
申请号 |
US20030355006 |
申请日期 |
2003.01.31 |
申请人 |
RENESAS TECHNOLOGY CORP.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
TOYOSHIMA HIROSHI;HAYASHI ATSUHIRO;NEGISHI TAKEMI;UEHARA TAKASHI |
分类号 |
G11C11/413;G11C11/41;H01L21/822;H01L21/8244;H01L23/528;H01L23/60;H01L25/04;H01L25/18;H01L27/04;H01L27/11;(IPC1-7):H01L27/10;H01L23/52 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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