| 摘要 |
<p>An internal clock generation circuit starts generation of an internal clock in response to reception of an external control signal via an input circuit. The external control signal indicates a request to access the memory core having a plurality of memory cells. A counter is composed of a plurality of bits and performs count operation in synchronization with the internal clock. An operation control circuit generates at least one of the operation control signals for controlling the memory core operation by combining the logic levels of bit output from the counter. By combining the logic levels of bit output from the counter, it is possible to generate a plurality of operation control signals. Accordingly, it is possible to reduce the circuit size of the operation control circuit. Since the delay circuit for defining the activation period of the operation control signal is not required any more, it is possible to minimize the semiconductor element manufacturing irregularities and affect of use condition fluctuation and surely generate the operation control signal at a desired timing. As a result, it is possible to prevent malfunction of the memory core.</p> |
