| 摘要 |
A device for correcting the duty cycle of a clock signal with a duty cycle modifying device which receives a clock signal and a complementary clock signal, which comprises a delay device for both clock signals, and which is adapted to generate a clock signal and a complementary clock signal with corrected duty cycle. The invention also relates to a corresponding method for correcting the duty cycle of a clock signal and may preferably be used to correct the duty cycle of the system clock input in a DDR-SDRAM device in order that an ideal duty cycle of 50 percent is achieved in the memory chip during the processing thereof to a data strobe. As compared to previous similar devices and methods, the invention thus enables, with DDR-SDRAM devices, a more precise reading out of the data from the devices to the system associated with the devices.
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