发明名称 |
Memory module and memory system |
摘要 |
In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. In this constitution, a wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip. |
申请公布号 |
US2004257847(A1) |
申请公布日期 |
2004.12.23 |
申请号 |
US20040828189 |
申请日期 |
2004.04.21 |
申请人 |
MATSUI YOSHINORI;SUGANO TOSHIO;IKEDA HIROAKI |
发明人 |
MATSUI YOSHINORI;SUGANO TOSHIO;IKEDA HIROAKI |
分类号 |
G06F12/00;G06F13/16;G11C5/00;G11C5/02;G11C5/06;G11C7/00;G11C7/10;H01L25/00;H01L25/065;H01L25/07;H01L25/18;(IPC1-7):G11C5/02 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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