SEMICONDUCTOR MEMORY DEVICE HAVING LATENCY CIRCUIT AND CONTROL METHOD FOR OUTPUTTING DATA, ESPECIALLY GENERATING LATENCY SIGNAL ACCORDING TO PLURAL SAMPLING CLOCK SIGNALS, A PLURAL TRANSFER SIGNALS AND PLURAL SAMPLING CLOCK SIGNALS

摘要

PURPOSE: A semiconductor memory device having a latency circuit and a control method for outputting data are provided to improve the processing speed by outputting latency signals according to an output clock signals for latched read signals after latching internal read signals using plural sampling clock signals. CONSTITUTION: A semiconductor memory device having latency circuit comprises a memory cell array(110); an output buffer(140) for receiving data from the memory cell array(110) and outputting received data from the memory cell array(110) in response to latency signals; a latency circuit(200) for timing matching each of plural sampling clock signals with a related transfer signal by selectively relating plural transfer signals to plural sampling clock signals in response to CAS latency, for storing read signals in response to at least one of plural sampling clock signals, and for generating latency signals in response to transfer signals related to the sampling clock signals used in storing the read signals.