发明名称 Multilevel cache system having unified cache tag memory
摘要 A unified tag subsystem for a multilevel cache memory system. The unified tag subsystem receives a cache line address including a tag index portion, a high order part and an optional cache line extension field. The tag index portion indexes a tag memory which has way-specific address tags, and lower level flags. A comparator compares the high order part with each way-specific address tag to detect a match. Lower level hit logic determines a hit when comparator detects a match and the lower level flag indicates a valid lower level cache entry; and an upper level hit logic determines a higher level cache hit when the comparator detects a match and the upper level valid is set. In particular embodiments, lower level flag indicates a way of storage where associated data may be found in lower level cache data memory.
申请公布号 US6834327(B2) 申请公布日期 2004.12.21
申请号 US20020071069 申请日期 2002.02.08
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 LYON TERRY
分类号 G06F12/00;G06F12/08;G06F13/00;(IPC1-7):G06F12/00 主分类号 G06F12/00
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