发明名称 System and method for reducing transitions on address buses
摘要 An encoder and decoder provide coding of information communicated on buses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus. The encoder and decoder may support logical partitioning of a memory space using fixed sector encoding or dynamic sector encoding,potentially coupled with other techniques such as reductions in the frequency of binary ones,transition signaling, and others.
申请公布号 US6834335(B2) 申请公布日期 2004.12.21
申请号 US20020215848 申请日期 2002.08.09
申请人 FUJITSU LIMITED;UNIVERSITY OF SOUTHERN CALIFORNIA 发明人 FALLAH FARZAN;AGHAGHIRI YAZDAN;PEDRAM MASSOUD
分类号 G06F12/02;(IPC1-7):G06F12/00 主分类号 G06F12/02
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