发明名称 |
Low-power phase-locked-loop and method |
摘要 |
A phase-locked loop includes a voltage-controlled oscillator (VCO) to generate a plurality of quadrature-phase signals at one-half an output frequency in response to bias signals. The VCO also includes a times-two multiplier biased by the bias signals to generate the output frequency from the quadrature-phase signals. The bias signals include a load-element bias signal to concurrently bias load elements of buffer stages of the VCO and substantially identical load elements of the multiplier. The bias signal also include a current-source bias signal to concurrently bias current sources of the buffer stages of the VCO and a substantially identical buffer stage of the multiplier. The VCO operating at one-half the output frequency together with the multiplier may consume less power than the VCO when operating at the output frequency.
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申请公布号 |
US2004251972(A1) |
申请公布日期 |
2004.12.16 |
申请号 |
US20030452444 |
申请日期 |
2003.06.02 |
申请人 |
INTEL CORPORATION |
发明人 |
AHMED RIZWAN |
分类号 |
H03B27/00;H03L7/00;H03L7/08;H03L7/089;H03L7/099;H03L7/18;(IPC1-7):H03L7/00 |
主分类号 |
H03B27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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