METHOD AND APPARATUS FOR ENHANCING THE SPEED OF A SYNCHRONOUS BUS

摘要

An apparatus (100) for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk (103) is supplied by the name PLL (11) that provides the main clock signal lg_clk (101). According to the invention, data is taken from the two registers in alternative clock cycles so that each of the register holds valid data for two clock cycles. A first software data bit is used to determine which of the two registers is unloaded first. Using the method and structure of the invention, the window for transferring valid data is increased and therefore the system employing the method and apparatus of the invention is more skew tolerant.