| 摘要 |
PROBLEM TO BE SOLVED: To enhance a surge resistance amount in J-FET. SOLUTION: A P-type epitaxial layer 2 and an N-type epitaxial layer 3 are formed on a P<SP>++</SP>conductive substrate 1, and an N<SP>+</SP>conductive source diffused layer 4, a drain diffused layer 5 and a P<SP>+</SP>conductive gate diffused layer 6 are formed on an N-type epitaxial layer 3. There is a short prevention layer 8 composed of an inverted conductive diffused layer so as to come into contact with an edge of the N<SP>+</SP>conductive source diffused layer 4 and the drain diffused layer 5, and an occurrence of a punch-through is suppressed in a surface region caused by a surge voltage to enhance a surge resistance amount. Here, a source electrode 10 connected to the source diffused layer 4 through an opening provided in a protection insulating film 9 and a drain electrode 11 connected to the drain diffused layer 5 are provided on a surface side, and also a gate electrode 12 contacted with the gate diffused layer 6 is provided through a contact diffused layer 7 on a back surface side of a board 1. COPYRIGHT: (C)2005,JPO&NCIPI
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