| 摘要 |
PROBLEM TO BE SOLVED: To suppress test costs by enabling a DC burn-in test using an equalizer circuit in place of a dynamic burn-in test. SOLUTION: A plurality of bit lines for inputting/outputting data for a memory cell 1 arranged in a matrix form are constituted of a plurality of bit line pairs BLP1 to BLP4 repeatedly arranged by setting two bit lines connected to the same sense amplifier as a pair. The two bit lines constituting the bit line pair are connected to different voltage supply lines 14 and 15 through bit line connection control transistors 11 and 12. Thus, the freedom of setting a burn-in voltage level is high, and a burn-in voltage (electric stress) is applied among all the bit lines. COPYRIGHT: (C)2005,JPO&NCIPI
|
