发明名称 |
Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits |
摘要 |
A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized and etched back. Next a barrier cap layer is deposited that is different than the underlying low k dielectric layer. In one embodiment, the barrier cap layer is a SiCOH material that is modified for enhanced CMP performance that yields fewer surface scratches and defects. A nitride etch stop layer and a pad oxide are removed above an active area on the substrate to afford the final STI structure. Optionally, the barrier cap layer is omitted and the low k dielectric layer extends slightly above the substrate level. Total parasitic capacitance in the resulting MOS device is reduced by 15% or more.
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申请公布号 |
US2004251513(A1) |
申请公布日期 |
2004.12.16 |
申请号 |
US20030462314 |
申请日期 |
2003.06.13 |
申请人 |
TAIWAN SEMICONDUTOR MANUFACTURING CO. |
发明人 |
SU KE-WEI;HSIAO CHENG;HER JAW-KANG |
分类号 |
H01L21/762;H01L21/8234;H01L29/78;(IPC1-7):H01L21/823;H01L29/00 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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