| 摘要 |
PROBLEM TO BE SOLVED: To simplify a process for cache coinciding control and confirm the completion of the control without degradation in the efficiency of an inner bus on a data transfer circuit side. SOLUTION: An area within a cache memory to be an object of coinciding control is preset to a resisters R1, R2 of a cache controller 125-1. A main controller 125a writes data transferred from a data transfer circuit into a cache memory 124-1. If the writing destination of the data belongs to the area specified by the resisters R1, R2, the data and the address corresponding thereto are transferred to other cache controller 125-2 by an inter-cache communication controller 125c and written into a cache memory 124-2 by the controller 125-2. When the writing in the memory 124-2 is completed, the state is reflected to a flag F12 in a resister R3 so that the state can be informed to the transfer circuit. COPYRIGHT: (C)2005,JPO&NCIPI
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