| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To increase the degree of integration by performing layout compaction with an optical proximity effect taken into consideration, even for layout patterns of irregular arrangements included in circuit design data. <P>SOLUTION: A compaction condition is generated in a compaction control step 2, an OPC condition is generated in an OPC condition generation step 8, compaction of an input layout pattern is performed in a layout compaction step 3, optical proximity effect correction is performed in an optical proximity effect correction step 4, the layout pattern after the optical proximity effect correction is held in a corrected layout pattern preservation step 5, circuit operation is confirmed with the layout pattern subjected to compaction and optical proximity effect correction in verification steps 6 and 10, the layout pattern is held in an error data preservation step 7 when having trouble, and a compaction condition with the optical proximity effect and error data taken into consideration is generated again in the compaction control step 2, and these steps are repeated. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
