发明名称 |
DETERMINISTIC ADDRESSING OF NANOSCALE DEVICES ASSEMBLED AT SUBLITHOGRAPHIC PITCHES |
摘要 |
<p>A method for constructing and addressing a nanoscale memory with known addresses and for tolerating defects which may arise during manufacture or device operational lifetime. During construction, nanoscale wires with addresses are stochastically assembled. During a programming phase, nanoscale wires are stochastically selected using their stochastic addresses through microscale inputs and a desired address code is associated with the selected nanoscale wires. Memory addresses are associated to the codes and then selected using the known codes during read/write operations from/to the memory.</p> |
申请公布号 |
WO2004109703(A1) |
申请公布日期 |
2004.12.16 |
申请号 |
WO2004US16572 |
申请日期 |
2004.05.26 |
申请人 |
CALIFORNIA INSTITUTE OF TECHNOLOGY;DEHON, ANDRE;NAEIMI, HELIA |
发明人 |
DEHON, ANDRE;NAEIMI, HELIA |
分类号 |
G11C8/10;G11C11/34;G11C13/02;G11C29/08;H03K19/177;(IPC1-7):G11C8/10 |
主分类号 |
G11C8/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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