发明名称 DELAY CONTROL CIRCUIT
摘要 PURPOSE:To reconcile the stability of high circuit operation and the high speed convergence to the stable point in the delay control circuit controlling the delay time for the signal by voltage. CONSTITUTION:Unit delay circuits I(1)-I(N) capable of changing the delay time by the voltage control are connected in a column. By inputting the start signal in the input, the delay time is detected in a time difference/potential conversion circuit S. This delay time and the setting value from a time difference/potential conversion circuit B are compared in binary discrimination circuits X1, X2 where the discrimination values are different. When the delay time is greatly different from the aimed delay time, it is detected in the both binary discrimination circuits X1, X2 and is tried so that the aimed value can be converged and obtained at a high speed by the synthetic output in each boosting/dropping circuit A1, A2. If the aimed value is approached in this way, it is detected only in the binary decision circuit X1 according to the difference of the decision value, the delay time is controlled and the stability of the high accuracy is obtained.
申请公布号 JPH04247714(A) 申请公布日期 1992.09.03
申请号 JP19910013203 申请日期 1991.02.04
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 ENDO KANICHI;MATSUMURA TSUNEO
分类号 G02B6/38;H03K5/13;H03K5/133 主分类号 G02B6/38
代理机构 代理人
主权项
地址