| 摘要 |
A phase-locked loop (PLL) circuit performing a fractional division includes a phase comparator circuit, a phase difference signal modulation circuit, and an oscillator circuit. The phase comparator circuit compares phases of two signals and outputs first and second phase difference signals. The phase difference signal modulation circuit modulates the second phase difference signals into third phase difference signals, and the oscillator circuit oscillates based on the first and third signals. |
