CLOCK DELAY CIRCUIT USING VARIABLE MOS CAPACITANCE TO CONTROL A PULSE WIDTH

摘要

PURPOSE: A clock delay circuit using a variable MOS capacitance is provided to control the delay amount of the clock signal by controlling the test signal or the voltage level of the connection test signal without physically being amended by the layout. CONSTITUTION: A clock delay circuit(200) using a variable MOS capacitance includes a connection line(CL) and a first to a nth MOS capacitors(MCAP1-MCAPn). The connection line connects the input node to input the clock signal and the output node to output the clock signal. The first to the nth MOS capacitors delay the clock outputted through the connection line connected to the connection line. Each of MOS capacitors has various gate capacitances corresponding to the first to the nth test signals.