| 摘要 |
A video signal is sampled in response to a sampling signal, and is fed to a data line. The sampling signal is generated based on an enable signal. A timing control circuit includes a group of delay circuits to delay a reference clock signal, a selector circuit to select signals in response to a selection signal, and an enable signal generator circuit to generate an enable signal based on an enable clock signal. The selection signal is generated based on a phase difference signal and has a constant fluctuation.
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