发明名称 |
Method and pattern for reducing interconnect failures |
摘要 |
A method and a pattern for reducing interconnect failures are described. The method and pattern are used for a multilevel structure of metal/dielectric/metal. At least one assistant pattern is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from generating at the bottom of a via plug which connects the two metal layers.
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申请公布号 |
US6831365(B1) |
申请公布日期 |
2004.12.14 |
申请号 |
US20030448656 |
申请日期 |
2003.05.30 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING, CO. |
发明人 |
YAO CHIH-HSIANG;WAN WEN-KAI;HUANG TAI-CHUN;HSIA CHIN-CHIU |
分类号 |
H01L23/522;H01L23/528;(IPC1-7):H01L23/48 |
主分类号 |
H01L23/522 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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