发明名称 Clock synchronization and fault protection for a telecommunications device
摘要 In one embodiment, a telecommunications device includes a synchronization bus and a controller coupled to the bus that generates a system clock signal according to a primary reference clock signal and communicates the system clock signal using the bus. The controller detects a loss of the primary reference clock signal and, in response, continues generating the system clock signal, determines acceptability of a secondary reference clock signal, switches from the primary reference clock signal to the secondary reference clock signal if the secondary reference clock signal is acceptable, and in response to the switch generates the system clock signal according to the secondary reference clock signal.
申请公布号 US6832347(B1) 申请公布日期 2004.12.14
申请号 US20030367523 申请日期 2003.02.14
申请人 CISCO TECHNOLOGY, INC. 发明人 PARRISH BRENT K.
分类号 G06F1/12;H04J3/06;(IPC1-7):G06F11/00 主分类号 G06F1/12
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