| 摘要 |
<p>PURPOSE: To provide a digital data multiplication processing circuit in which the number of multiplication devices can be reduced, and a chip size can be reduced. CONSTITUTION: This circuit is provided with a double clock alternate sampler 30 which alternately operates the sampling of (n) bit digital data impressed from plural input buses by a first system clock, two coefficient alternate multiplier 40 which alternately executes the multiplying processing of the digital data of each bus sampling-processed by the double clock alternate sampler and a coefficient corresponding to the digital data by the first system clock and first and second primary clocks, and data restorer 50 which separates the multiplied data of the two coefficient alternate multiplier by the first and second system clocks and the second primary clock for each input data, and outputs the data to plural output buses. Thus, the multiplying processing of the digital data inputted to the plural input buses can be attained by one multiplier.</p> |
