| 摘要 |
<p>PURPOSE:To reduce hardware of a system where memories are duplexed, reliability is improved and duplex writing and individual reading are possible, to execute duplex writing and individual reading by means of duplex CPU cards to permit plural CPU to simultaneously access to the different memories. CONSTITUTION:In the respective cases of duplex write time, memory 1104 read time and memory 1105 read time, the respective memories are selected by a chip selection system. A chip selection signal for the memories decodes not only an address bus also a signal showing whether access is from the other system or not and a signal identifying writing and reading. One CPU bus is divided into the number of the memories in a bydirectional gate and a bus arbiter receives and judges the output signals of respective address decoders.</p> |
