| 摘要 |
A sigma-delta analog-to-digital converter (10) having DEM (14) facilitated data weighted averaging to select specific unit elements of a negative feedback loop digital-to-analog converter (15), which DEM (14) is comprised substantially of transmission gates that contribute little to propagation delay. As a result, the feedback signal provided by the feedback loop is not more than one clock cycle behind the present coded output of the ADC (10) itself. As a result, higher resolution converters can be realized. The DEM (14) utilizes a repeating sequence to select specific unit elements. In some embodiments the direction of sequence usage is reversed in various ways to aid in reducing harmonic distortion.
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