MEMORY DEVICE FOR IMPLEMENTING 2N BIT PREFETCH SCHEME USING N BIT PREFETCH STRUCTURE, METHOD FOR PREFETCHING 2N BIT OF THE SAME AND AUTO-PRECHARGE METHOD, ESPECIALLY CONTROLLING THE TIME OF AUTO PRECHARGE BASED ON THE CHANGE OF A BURST LENGTH

摘要

PURPOSE: A memory device for implementing 2N bit prefetch scheme using N bit prefetch structure, a method for prefetching 2N bit of the same and an auto-precharge method are provided to allow the ultra high speed operation by implementing the 8 bit prefetch scheme with 4 bit prefetch structure without increasing the chip size. CONSTITUTION: A memory device for implementing 2N bit prefetch scheme using N bit prefetch structure includes a first parallel stage(500), a second parallel stage(600), a plurality of write data buffers(532,534), a plurality of write data buffers(536,538), a plurality of first switches(522,524) and a plurality of second switches(542,544). The first parallel stage receives the input data corresponding to the burst length N in response to the first write command and outputs the received data as a first parallel data. The second parallel stage receives the input data corresponding to burst length N in response to the first write command and outputs the received data as a second parallel data. The plurality of write data buffers stores the first parallel data in response to the first write control signal. The plurality of write data buffers stores the second parallel data in response to the second write control signal. The plurality of first switches transmits the data stores on the first write data buffers to the memory core block in response to the first switching signal. And, the plurality of second switches transmits the data stored on the second write data buffers in response to the second switching signals.