Integrated semiconductor memory has memory cell with inversion channel and small gate dielectric thickness permitting thermal majority carriers to tunnel to gate electrode

摘要

An integrated semiconductor memory cell (1) comprises at least one transistor (3) with an inversion channel when on and two source/drain regions (5,6) with semiconductor (4) between them and a gate (7,8) above a dielectric (9). A thin dielectric region provides a high resistance tunnel to the gate for thermally produced majority carriers when off.