发明名称 CLOCK SIGNAL DISTRIBUTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To average the accumulation value of the peak value of a feedthrough current generated in each circuit block, and to avoid noise having an inherent phase, in a semiconductor integrated circuit having a plurality of circuit blocks. <P>SOLUTION: In the semiconductor integrated circuit 1, a selection signal generation random number generation circuit 42 generates a selection signal S that changes randomly in a set range each time when an inverted signal U rises, a selector 43 switches input and output ends, where delay clock signals C<SB>1</SB>, C<SB>2</SB>, and C<SB>3</SB>are inputted according to details instructed by the selection signal S, and randomly supplies delay clock signal each having a different delay time for each circuit block. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p>
申请公布号 JP2004348466(A) 申请公布日期 2004.12.09
申请号 JP20030145189 申请日期 2003.05.22
申请人 KONICA MINOLTA BUSINESS TECHNOLOGIES INC 发明人 HIROZAWA SAKURA
分类号 G06F1/04;G06F1/10;H03K5/15;H03K17/16;(IPC1-7):G06F1/10 主分类号 G06F1/04
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