发明名称 METHOD FOR SIMULATION OF ELECTRONIC CIRCUITS AND N-PORT SYSTEMS
摘要 According to an embodiment of the invention, a system and method for performing simulations is provided. Using parallelism in systems, the method decomposes a larger problem into several smaller partitions. A series of iterations is performed until the waveforms exchanged between the partitions converge. Approximate pre­view solutions of strongly coupled partitions are introduced to reduce the number of iterations required for convergence. These approximate pre-view solutions are introduced before the simulations occur. Once the waveforms converge, the simulation has determined a solution.
申请公布号 WO2004107828(A2) 申请公布日期 2004.12.09
申请号 WO2004US16384 申请日期 2004.05.24
申请人 VERISILICA, INC.;SHAH, SUNIL, C. 发明人 SHAH, SUNIL, C.
分类号 G06F17/10;G06F17/50;H05K 主分类号 G06F17/10
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