发明名称 SEMICONDUCTOR DEVICE AND DESIGN METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To suppress reduction of a degree of circuit integration by the enlargement of the interval of signal lines, and by inserting a shield line or a shielding layer between the signal lines, and to prevent malfunctions of the circuit due to noise. SOLUTION: The device has a multilayer wiring structure, in which three or more wiring layers are stacked on a silicon semiconductor substrate, and is equipped with a first signal line 12 which is formed by a (N-1)-th wiring layer, and constitutes a latch circuit, a second signal line 13 which has a part arranged being crossed or overlapped partially the first signal line 12, and formed by a (N+1)-th wiring layer, and a power line 14 which is formed by a N-th wiring layer between the first signal line 12 and the second signal line 13, and on the just lower portion of the second signal line 13, and functions as a shield wiring. The noise generated by voltage fluctuation of the second signal line 13 is shielded with the power line 14, and the malfunction of the latch circuit can be prevented; and a shield wiring need not be provided separately from the power line 14. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004349681(A) 申请公布日期 2004.12.09
申请号 JP20040085027 申请日期 2004.03.23
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KATSURA AKIHITO;YAMAMOTO HIROO
分类号 H01L27/04;H01L21/82;H01L21/822;(IPC1-7):H01L21/82 主分类号 H01L27/04
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