| 摘要 |
PROBLEM TO BE SOLVED: To improve the flatness of an interlayer insulation film and reduce, at the same time, a parasitic capacitance generated between wiring and a semiconductor substrate. SOLUTION: In the region wherein gate electrodes 3n of n-channel MISFETs (metal insulator semiconductor field effect transisters) Qn are scarcely existent, there are disposed dummy patterns 4a comprising the insulation films formed out of the same layer as sidewalls 4 formed on the sidewalls of the gate electrodes 3n of the n-channel MISFETs Qn. Thereafter, the upper layer of the gate electrodes 3n is covered with an interlayer insulation film 5, and the surface of the interlayer insulation film 5 is so polished by a CMP (chemical and mechanical polishing) method as to flatten it. In this way, since the surface of the interlayer insulation film 5 is polished after the disposals of the dummy patterns 4a, the flatness of the interlayer insulation film 5 can be improved. Also, in comparison with the case of disposing at the same time dummy bedding patterns comprising conductors in the foregoing region, the parasitic capacitance generated between a semiconductor substrate 1 and wiring 8 can be reduced. COPYRIGHT: (C)2005,JPO&NCIPI
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