发明名称 |
METHOD FOR DESIGNING POWER WIRING OF SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for designing power wiring for resolving the problem of supply voltage reduction in a semiconductor integrated circuit, which arises as finely divided processes are accelerated in manufacturing a semiconductor. SOLUTION: The method comprises estimating (step 12) the number and width of wiring of individual components as conditions for designing a mesh structure of the power wiring, and designing a layout (step 13) for the mesh power wiring based on the number and width of wiring of the individual components. By attaining high precision estimation of the model of the power wiring structure with this top-down designing, reduction rate of supply voltage is suppressed. COPYRIGHT: (C)2005,JPO&NCIPI
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申请公布号 |
JP2004349436(A) |
申请公布日期 |
2004.12.09 |
申请号 |
JP20030144337 |
申请日期 |
2003.05.22 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
KUSUMOTO KEIICHI;SAIGA SHUNJI;HIRATA AKIO;NISHIMURA HIDETOSHI |
分类号 |
G06F17/50;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H01L21/82 |
主分类号 |
G06F17/50 |
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主权项 |
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