FERROELECTRIC MEMORY

摘要

For a predetermined period of time after start of read out operation, current is supplied to a bit line connected to a memory cell and a ferroelectric capacitor of the memory cell is charged. Voltage change of the bit line varies according to the logic value of data written in the ferroelectric capacitor. Accordingly, it is possible to detect the logic value of the data stored in the memory cell as a time difference. Even when the voltage change of the bit line is small, it is possible to generate a time difference without fail. Consequently, even when the ferromagnetic capacitor has a small residual polarization value, it is possible to surely read out data from the memory cell. That is, as compared to detection of a logic value of data by a voltage difference, it is possible to enhance the data read out margin.