| 摘要 |
PROBLEM TO BE SOLVED: To provide a synchronizing digital signal processing system capable of reducing firmware for detecting an unloaded package and power consumption, automatically supplying a clock signal at the time of restoration and simplifying and reducing a clock signal sending circuit. SOLUTION: Each package(PKG) 2X (X=1 to N) has a buffer 3X (X=1 to N) for entering an inputted clock signal into its inside and outputting the clock signal to the outside, a short-circuit part 4X (X=1 to N) having a wiring for short-circuiting an input and an output and directly connecting inputted/ outputted driving signals in its inside and an alarm output part 5X (X=1 to N) for setting up the alarm state of its own PKG to an initial state by the disappearance of a driving signal input and masking an alarm output. Wiring among the PKGs is executed by successively sending a clock signal outputted from one clock sending part 12 by successively connecting the buffers 3X in the PKGs 2X in series and opening the final buffer 3N and sending an alarm output drive signal by successively connecting the short-circuit parts 4X in the PKGs 2X in series and connecting the final short-circuit part 4N to the alarm output parts 5X in all the PKGs 2X. |
