发明名称 ACTIVE LOAD CIRCUIT
摘要 PROBLEM TO BE SOLVED: To enhance the mutual conductance of an active load circuit without increasing the consumption of a load current and without enlarging a chip occupied area. SOLUTION: An active load circuit is composed of a first main current generation circuit 1 which generates a first load current, a first sub-current generation circuit 3 which generates a load current of a predetermined ratio for the value of the first load current, a second main current generation circuit 2 which generates a second load current, and a second sub-current generation circuit 4 which generates a load current of a predetermined ratio for the value of the second load current. An output terminal 12 which outputs the current from the first main current generation circuit 1 and an output terminal 42 which outputs the current of the second sub-current generation circuit 4 are commonly connected, and an output terminal 22 which outputs the current from the second main current generation circuit 2 and an output terminal 32 which outputs the current of the first sub-current generation circuit 3 are commonly connected. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004350197(A) 申请公布日期 2004.12.09
申请号 JP20030147521 申请日期 2003.05.26
申请人 YASU SEMICONDUCTOR CORP 发明人 TAKADA SHIGEO
分类号 H03F3/45;(IPC1-7):H03F3/45 主分类号 H03F3/45
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