发明名称 CLOCK SWITCHING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To surely switch two clocks by selecting a first clock when the first clock and a second clock are input and the first clock is not cut, according to an output signal of flip-flop circuit, and selecting the second clock by a selection circuit when the first clock is not cut, then outputting it. SOLUTION: When a first clock is not cut, the first clock is selected by a selection circuit 9 and then outputting it, and when cut, a second clock is selected and the outputting it. A clock switching circuit has a logical sum of output signals of first and second signal reception processing means by first and second logical sum circuits 2, 4, and even when the first clock is cut, the circuit 9 is operated so that signals to a clock monitoring circuit 7 and a flip flop circuit 8 are not stopped. With the first and second signal reception processing means both clocks are converted into those of 1/2 cycle, and the flip flop circuit 8 operates with the phase delayed by 90 degrees.
申请公布号 JPH09257963(A) 申请公布日期 1997.10.03
申请号 JP19960066391 申请日期 1996.03.22
申请人 NEC CORP 发明人 ONO YOSHIAKI;TANAKA HIROTADA
分类号 G04F10/04;H04L1/22;H04L7/00 主分类号 G04F10/04
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