REGISTER CONTROLLED DELAY LOCKED LOOP WITH LOW POWER CONSUMPTION, IN WHICH A DELAY LINE ARE COMPOSED OF A PLURALITY OF DELAY GROUPS HAVING SEVERAL UNIT DELAYS

摘要

PURPOSE: A register controlled delay locked loop with low power consumption is provided to drastically reduce the undesired current consumption of the digital DLL. CONSTITUTION: A register controlled delay locked loop with low power consumption includes a clock generation unit, a first and a second delay lines(22,23), a delay model(25), a phase comparison unit(26), a delay controller(27) and a first and a second clock input controllers(28,29). The clock generation unit generates a source clock, a delay monitoring clock and a reference clock. The first and the second delay lines delay the source clock and the delay monitoring clock. The delay model inputs the outputs of the second delay line as an input and performs the modeling of the delay components of the practical clock. The phase comparison unit compares the feedback clock outputted from the delay model with the phase of the reference clock. The delay controller controls the delay amount of the first and the second delay lines in response to the comparison reason of the phase comparison unit. And, the first and the second clock input controllers selectively supplying the source clock and delay monitoring clock to one of the first and the second delay groups in response to the output of the delay controller.