发明名称 SEMICONDUCTOR MEMORY, SEMICONDUCTOR MEMORY SYSTEM AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce the number of bit lines, prevent generation of an irregular current by a random data to avoid irregular operation and failure by using in common the bit lines of the adjacent columns in the same row and selecting the adjacent columns with different word lines. SOLUTION: In the same row, memory cells M1 to M4 are arranged, bit lines (BL) 1 and 2 are arranged to the cell M1, while BL2 and BL3 to the cell M2, BL3 and BL4 to the cell M3, BL4 and BL5 to the cell M3 and BL4 and BL5 to the cell M4. Namely, one BL is used in common between the memory cells of the adjacent odd and even number columns and two word lines (WL) are wire per row address. Since the cells M1, M3 of the odd number columns are connected to WL1, while the cells M2, M4 of the even number columns are connected to WL2, only the N+1 BLs per N columns are enough. Thereby, the number of BL can be reduced and generation of irregular current due to the random data when the power is turned ON can be prevented in order to prevent irregular operation and breakdown.
申请公布号 JPH1092181(A) 申请公布日期 1998.04.10
申请号 JP19960244627 申请日期 1996.09.17
申请人 TOSHIBA CORP 发明人 MUROGA HIROKI;MIZUTA MASARU
分类号 G11C11/41;H01L21/822;H01L21/8244;H01L27/04;H01L27/11 主分类号 G11C11/41
代理机构 代理人
主权项
地址