| 摘要 |
PURPOSE: A register controlled delay locked loop(DLL) provided with an acceleration mode is provided to improve the operational characteristics of the DLL by preventing the delay locked time from increasing at the DLL in a low operational frequency. CONSTITUTION: A register controlled delay locked loop(DLL) provided with an acceleration mode includes a pair of delay lines(54,55), a delay model(59), a first phase comparison unit(60), a second phase comparison unit(64), a shift register controller(61), a controller(66) and a shift register(62). The delay model reflects the delay condition of the practical clock path on the inner clock passing through the delay lines. The first phase comparison unit compares the output signal of the delay model with the phase of the inner clock. The second phase comparison unit compares the output signal of the delay unit with the phase of the inner clock. The shift register controller outputs the shift left signal, shift right signal and an acceleration shift signal in response to the output signals of the first phase comparison unit and the mode determination unit. The controller(66) controls the unit delay amount at the acceleration mode in response to the operational frequency information. And, the shift register controls the delay amount of the delay lines in response to the outputs of the shift register controller and the controller(66).
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