| 摘要 |
<p>In the case in which a former half part of a transmission packet is subjected to FSK modulation transmission and a latter half thereof is subjected to PSK modulation transmission, to correct frequency shift in a short preamble period at the time of PSK demodulation and lock up a phase locked loop. In the case in which a former half part of a transmission packet is sent by an FSK modulating signal, and a latter half part thereof is sent by a PSK modulating signal, a received signal is converted into an intermediate frequency signal by a mixer 2, the converted intermediate frequency signal is switched to an FSK demodulation unit 6 and a PSK demodulation unit 7 by a received signal changeover switch 5. A frequency error detection circuit 14 is provided in the FSK demodulation unit 6 to detect a frequency error detection value fe. A demodulation circuit 24 of a phase locked loop type of the PSK demodulation unit 7 includes a loop filter 29. The frequency error detection value fe detected by the frequency error detection circuit 14 is set as an initial value of this loop filter 29, whereby a time until lockup of a phase locked loop is reduced at the time when reception of a PSK modulating signal is started. <IMAGE></p> |
