| 摘要 |
A phase locked loop (PLL) frequency synthesizer has a phase comparator, a voltage-controlled oscillator, a charge pump circuit, a loop filter, a variable frequency divider periodically changing a division value in response to a frequency division value changing circuit, and a charge pump bias circuit for supplying a modulated reference bias current, for canceling a phase error, to the charge pump circuit. As a result, without generating additional spurious components, conventionally-generated spurious components can be suppressed.
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